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1 h a l o g e n f r e e tm l e a d f r e e cs sk di do v cc rdy/busy reset gnd 1 2 3 4 8 7 6 5 cs sk di do v cc rdy/busy reset gnd 1 2 3 4 8 7 6 5 rdy/busy v cc cs sk reset gnd do di 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 cs sk di do v cc rdy/ bus y reset gnd 1 2 3 4 8 7 6 5 rdy/ busy v cc cs sk reset gnd do di cat64lc10/20/40 1k/2k/4k-bit spi serial eeprom features spi bus compatible low power cmos technology 2.5v to 6.0v operation self-timed write cycle with auto-clear hardware reset pin hardware and software write protection commercial, industrial and automotive temperature ranges power-up inadvertant write protection rdy/ bsy bsy bsy bsy bsy pin for end-of-write indication 1,000,000 program/erase cycles 100 year data retention description the cat64lc10/20/40 is a 1k/2k/4k-bit serial eeprom which is configured as 64/128/256 registers by 16 bits. each register can be written (or read) serially by using the di (or do) pin. the cat64lc10/20/40 is manufactured using catalyst? advanced cmos eeprom floating gate technology. it is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. the device is available in 8-pin dip, soic and tssop packages. block diagram pin configuration dip package (p, l) soic package (j, w) tssop package (u, y) pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +2.5v to +6.0v power supply gnd ground reset reset rdy/busy ready/busy status ?2004 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1021, rev. b soic package (s, v) tssop package (ur, yr) 64lc10/20/40 f02 v cc address decoder memory array 64/128/256 x 16 data register mode decode logic clock generator output buffer do sk cs di reset gnd rdy/busy
2 cat64lc10/20/40 doc. no. 1021, rev. b absolute maximum ratings* temperature under bias ................. ?5 c to +125 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to ground (1) ............ ?.0v to +v cc +2.0v v cc with respect to ground ............... ?.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min. max. unitsreference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 capacitance (t a = 25 c, f= 1.0 mhz, v cc =6.0v) symbol test max. units conditions c i/o (3) input/output capacitance (do, rdy/ bsy )8pfv i/o = 0v c in (3) input capacitance ( cs , sk, di, reset) 6 pf v in = 0v note: (1) the minimum dc input voltage is ?.5v. during transitions, inputs may undershoot to ?.0v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from ?v to v cc +1v.
3 cat64lc10/20/40 doc. no. 1021, rev. b d.c. operating characteristics v cc = +2.5v to +6.0v, unless otherwise specified. note: (1) v oh and v ol spec applies to ready/ busy pin also limits sym. parameter min. typ. max. unitstest conditions i cc operating current 2.5v 0.4 ma f sk = 250 khz ewen, ewds, read 6.0v 1 ma f sk = 1 mhz i ccp program current 2.5v 2 ma 6.0v 3 ma i sb (1) standby current 1 av in = gnd or v cc cs = v cc i li input leakage current 2 av in = gnd to v cc i lo output leakage current 10 av out = gnd to v cc v il low level input voltage, di ?.1 v cc x 0.3 v v ih high level input voltage, di v cc x 0.7 v cc + 0.5 v v il low level input voltage, ?.1 v cc x 0.2 v cs , sk, reset v ih high level input voltage, v cc x 0.8 v cc + 0.5 v cs , sk, reset v oh (1) high level output voltage 2.5v v cc ?0.3 v i oh = ?0 a 6.0v v cc ?0.3 v i oh = ?0 a 2.4 v i oh = ?00 a v ol (1) low level output voltage 2.5v 0.4 v i ol = 10 a 6.0v 0.4 v i ol = 2.1ma
4 cat64lc10/20/40 doc. no. 1021, rev. b note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) this parameter is sampled but not 100% tested. (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. write cycle limiits symbol parameter min. max. units t wr program cycle time 2.5v 10 ms 4.5v?.0v 5 a.c. operating characteristics v cc = +2.5v to +6.0v, unless otherwise specified. limits symbol parameter min. typ. max. units t css cs setup time 100 ns t csh cs hold time 100 ns t dis di setup time 200 ns t dih di hold time 200 ns t pd1 output delay to 1 300 ns t pd0 output delay to 0 300 ns t hz (2) output delay to high impendance 500 ns t csmin minimum cs high time 250 ns t skhi minimum sk high time 2.5v 1000 ns 4.5v?.0v 400 t sklow minimum sk low time 2.5v 1000 ns 4.5v?.0v 400 t sv output delay to status valid 500 ns f sk maximum clock frequency 2.5v 250 khz 4.5v?.0v 1000 t ress reset to cs setup time 0 ns t resmin minimum reset high time 250 ns t resh reset to ready hold time 0 ns t rc write recovery 100 ns power-up timing (1)(3) symbol parameter min. max. units t pur power-up to read operation 10 s t puw power-up to program operation 1 ms
5 cat64lc10/20/40 doc. no. 1021, rev. b instruction set instruction opcode address data read 64lc10 10101000 a5 a4 a3 a2 a1 a0 0 0 d15 - d0 64lc20 10101000 a6 a5 a4 a3 a2 a1 a0 0 d15 - d0 64lc40 10101000 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 write 64lc10 10100100 a5 a4 a3 a2 a1 a0 0 0 d15 - d0 64lc20 10100100 a6 a5 a4 a3 a2 a1 a0 0 d15 - d0 64lc40 10100100 a7 a6 a5 a4 a3 a2 a1 a0 d15 - d0 write enable 10100011 x x x x x x x x write disable 10100000 x x x x x x x x [write all locations] (1) 10100001 x x x x x x x x d15?0 figure 1. a.c. testing input/output waveform (2)(3(4) (c l = 100 pf) note: (1) (write all locations) is a test mode operation and is therefore not included in the a.c./d.c. operations specifications. (2) input rise and fall times (10% to 90%) < 10 ns. (3) input pulse levels = v cc x 0.2 and v cc x 0.8. (4) input and output timing reference = v cc x 0.3 and v cc x 0.7. input pulse levels reference points v cc x 0.7 v cc x 0.3 v cc x 0.8 v cc x 0.2
6 cat64lc10/20/40 doc. no. 1021, rev. b device operation the cat64lc10/20/40 is a 1k/2k/4k-bit nonvolatile memory intended for use with all standard controllers. the cat64lc10/20/40 is organized in a 64/128/256 x 16 format. all instructions are based on an 8-bit format. there are four 16-bit instructions: read, write, ewen, and ewds. the cat64lc10/20/40 operates on a single power supply ranging from 2.5v to 6.0v and it has an on- chip voltage generator to provide the high voltage needed during a programming operation. instructions, addresses and data to be written are clocked into the di pin on the rising edge of the sk clock. the do pin is normally in a high impedance state except when outputting data in a read operation or outputting rdy/ bsy status when polled during a write operation. the format for all instructions sent to this device includes a 4-bit start sequence, 1010, a 4-bit op code and an 8- bit address field or dummy bits. for a write operation, figure 2. sychronous data timing figure 3. read instruction timing * please check the instruction set table for address sk di cs do t pd0, t pd1 t css t dis t skhi t sklow reset rdy/ busy t ress t rc t dih t csh t csmin t hz t sv t sv t resh sk di cs do reset 10101000 address* d15 d14 d1 d0 high rdy/ busy
7 cat64lc10/20/40 doc. no. 1021, rev. b a 16-bit data field is also required following the 8-bit address field. the cat64lc10/20/40 requires an active low cs in order to be selected. each instruction must be preceded by a high-to-low transition of cs before the input of the 4-bit start sequence. prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence. figure 4. write instruction timing figure 5. ready/ busy busy busy busy busy status instruction timing read upon receiving a read command and address (clocked into the di pin), the do pin will output data one t pd after the falling edge of the 16th clock (the last bit of the address field). the read operation is not affected by the reset input. write after receiving a write op code, address and data, the device goes into the auto-clear cycle and then the * please check instruction set table for address sk di cs do reset 10100100 address* d15 d0 rdy/ busy sk di cs do reset write instruction next instruction high low rdy/ busy
8 cat64lc10/20/40 doc. no. 1021, rev. b write cycle. the rdy/ bsy pin will output the busy status (low) one t sv after the rising edge of the 32nd clock (the last data bit) and will stay low until the write cycle is complete. then it will output a logical ??until the next write cycle. the rdy/ bsy output is not affected by the input of cs . an alternative to get rdy/ bsy status is from the do pin. during a write cycle, asserting a low input to the cs pin will cause the do pin to output the rdy/ bsy status. bringing cs high will bring the do pin back to a high impedance state again. after the device has completed a write cycle, the do pin will output a logical ??when the device is deselected. the rising edge of the first ? input on the di pin will reset do back to the high impedance state again. the write operation can be halted anywhere in the operation by the reset input. if a reset pulse occurs during a write operation, the device will abort the operation and output a ready status. note: data may be corrupted if a reset occurs while the device is busy . if the reset occurs before the busy period, no writing will be initiated. however, if reset occurs after the busy period, new data will have been written over the old data. figure 6. reset during busy busy busy busy busy instruction timing figure 7. ewen instruction timing 5064 fhd f09 * please check instruction set table for address sk di cs do reset 10100100 address* d15 d0 t wr rdy/ busy sk di cs do reset 10100011 high-z high rdy/ busy
9 cat64lc10/20/40 doc. no. 1021, rev. b reset the reset pin, when set to high, will reset or abort a write operation. when reset is set to high while the write instruction is being entered, the device will not execute the write instruction and will keep do in high- z condition. when reset is set to high, while the device is in a clear/write cycle, the device will abort the operation and will display ready status on the rdy/ bsy pin and on the do pin if cs is low. the reset input affects only the write and write all operations. it does not reset any other operations such as read, ewen and ewds. erase/write enable and disable the cat64lc10/20/40 powers up in the erase/write disabled state. after power-up or while the device is in an erase/write disabled state, any write operation must be preceded by an execution of the ewen instruction. once enabled, the device will stay enabled until an ewds has been executed or a power-down has occured. the ewds is used to prevent any inadvertent over- writing of the data. the ewen and ewds instructions have no affect on the read operation and are not affected by the reset input. figure 8. ewds instruction timing sk di cs do reset 10100000 high-z high rdy/ busy
10 cat64lc10/20/40 doc. no. 1021, rev. b ordering information notes: (1) the device used in the above example is a 64lc10si-te13 (soic, industrial temperature, tape & reel) p: pdip s: soic (jedec) j: soic (jedec) u: tssop ur: tssop (rotated) l: pdip (lead free, halogen free) v: soic (jedec) (lead free, halogen free) w: soic (jedec) (lead free, halogen free) y: tssop (lead free, halogen free) yr: tssop (rotated) (lead free, halogen free)
11 cat64lc10/20/40 doc. no. 1021, rev. b packaging information 8-lead tssop (u) 7.72 typ 4.16 typ (1.78 typ) 0.42 typ 0.65 typ land p a ttern recommend a tion -a- -b- 3.2 6.4 a b c 0.2 8 5 3.0 + 0.1 4.4 + 0.1 all lead tips pin #1 ident. 1 4 all lead tips 1.1 max typ 0.1 c (0.9) 0.10 + 0.05 typ 0.19 - 0.30 typ 0.3 m a b s c s 0.65 typ see detail a 0.09 - 0.20 typ 0.6+0.1 seating plane gage plane 0.25 0 o - 8 o detail a -c-
12 cat64lc10/20/40 doc. no. 1021, rev. b catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1021 revison: b issue date: 9/3/04 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 9/3/2004 b added green packages in all areas updated dc operating characteristics table & notes

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